chip area造句
例句与造句
- The chipped area is not between the lugs of adjacent positive and negative plates .
破碎部分不在相邻的正负极耳之间。 - Its circuit structure is very complex and its chip area is restricted severely by the client
其电路结构十分复杂，而且客户又对版图面积做了详细的规定。 - The chip area and power savings of not implementing floating - point in hardware can be critical in embedded microprocessors
在嵌入式微处理器中，硬件中省去浮点（支持）而为实现带来的芯片面积和功率的减少是至关重要的。 - The dual mode transmitter can be configured in voltage mode supporting 12mbp / s data rate or current mode supporting 480mbp / s data rate . it reduces greatly the chip area resulting from this architecture
双模发送器的设计，采用电压模式和电流模式实现了全速( 12mbp s )和高速( 480mbp s )模式的兼容，取代了传统的全速和高速发送器分开设计的模式，大大节省了芯片的面积。 - Since the multiplication calculation cost more chip area than add calculation and the floationg - point calculations are not efficiently implemented in custom hardware they were replaced by scaled fixed - point approximations . also the jpeg coding algorithm requires a substantial amount of memory
本设计只在dct变换部分实现了必要数目的乘法器，通过采用特定的量化表避免了在量化模块中进行除法运算，大大减少了乘法器的数量。 - It's difficult to find chip area in a sentence. 用chip area造句挺难的
- Circuit design is the basis of design of demultiplexer . speed , power and chip area are the main factors that should be considered in circuit design . every circuit structure has its merits and drawbacks , e . g . cmos logic family has a slower speed , but lower power , smaller area , scfl ( source couple fet logic ) family has a higher speed , but higher power , larger area . we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors . flip - flop is the fundamental element of demultiplexer , setup time and hold up time are key factors , which influence the speed of circuit , thus the design aim is how to reduce them . in this thesis we place emphasis on the design of scfl latches
速度、功耗、面积是电路设计要考虑的主要因素，不同的电路形式具有不同的优缺点，如cmos互补逻辑电路功耗低，面积小，速度相对较慢； scfl (源极耦合fet逻辑)电路速度高，功耗和面积较大。所以要针对具体设计需要选用适当的电路形式或其组合结构，以满足设计要求。触发器是分接器的基本组成单元，建立时间和保持时间是影响电路速度的关键，所以减小建立时间和保持时间是触发器设计的主要目标，本文着重介绍了scfl锁存器的设计和优化方法。 - At the logic synthesis stage , we make some research on the principles of logic synthesis at first , then by utilizing tsmc0 . 25um process , choosing the worst case that the workable temperature can be high to 125 degrees centigrade and the supply voltage is as low as 2 . 25v , and introducing the wireload library for effectively simulating delay and power consumption of wire connection , and taking the same clocks as in simulation , the critical path is 15 . 3ns and the chip area is 0 . 395mm2
在进行逻辑综合时首先对逻辑综合的原理作了一定的了解，然后利用tsmc的0 . 25 m的工艺库，工作电压为2 . 25v ，工作温度最高可达到125摄氏度的最坏情况下，进行逻辑综合时引入了wireload库以便有效的模拟连线所引起的延迟及功耗，采用与模拟时相同的时钟，关键路径为15 . 3ns ，芯片面积为0 . 395mm ~ 2 。 - Firstly , based on conventional vq , a fast algorithm named equal - sum block - extending nearest neighbor search ( ebnns ) is presented , which not only can achieve the reconstructed image of full search algorithm but also can greatly reduce both the codeword search ratio and chip area . in order to improve coding efficiency , a new algorithm called correlation - inheritance coding is proposed , which is embedded in conventional vq system to improve compression ratio by re - encoding the indexes
首先，在普通矢量量化基础上提出了等和值块扩展最近邻快速码字搜索算法( ebnns ) ，该算法在图像画质达到穷尽搜索算法的前提下，大大降低了码字搜索率和硬件实现面积；为了提高编码效率，在相关性编码方面，提出了相关继承编码算法，对普通矢量量化后的编码索引进行无损重编码。 - The hspice simulation result shows a temperature coefficient of 11 ppm / " c from - 40 ? to 100 ' c and output voltage variation of 1mv for supply voltage range from 8 v to 18 v . due to novel curvature compensation , the circuit structure of the proposed reference is simple and both chip area and power consumption are small
Hspice仿真结果显示：该基准源在- 40 100的温度变化范围内，具有11ppm的低温度系数；当电源电压在8 18v变化时，输出电压变化量仅为1mv ；并且电路结构简单，具有较小的芯片面积和功耗。